2018-12-16 13:27:29 +03:00
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/*
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Copyright 2018 0KIMS association.
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This file is part of circom (Zero Knowledge Circuit Compiler).
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circom is a free software: you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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circom is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with circom. If not, see <https://www.gnu.org/licenses/>.
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*/
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2018-12-15 11:00:35 +03:00
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/*
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Each level in the SMTVerifier has a state.
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This is the state machine.
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The signals are
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levIns: 1 if we are in the level where the insertion should happen
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xor: 1 if the bitKey of the old and new keys are different in this level
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is0: Input that indicates that the oldKey is 0
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fnc: 0 -> VERIFY INCLUSION
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1 -> VERIFY NOT INCLUSION
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err state is not a state itself. It's a lack of state.
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The end of the last level will have to be `na`
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2018-12-15 11:15:58 +03:00
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levIns=0 any
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┌────┐ ┌────┐
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│ │ │ │
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│ ▼ levIns=1 ▼ │
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│ ########### is0=1 ########### ########### │
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│ # # fnc=1 # # any # # │
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└──# top # ─────────────────────▶# i0 #───────────────▶# na #──┘
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## ## ──────────┐ ## ## ┌───────▶## ##
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########─────────────┐│ ######### │┌────────▶#########
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││ levIns=1 ││
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││ is0=0 ########### ││
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││ fnc=1 # # any│
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│└──────────▶ # iold #────────┘│
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│ ## ## │
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│ ######### │
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│ │
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│ levIns=1 ########### │
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│ fnc=0 # # any
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└────────────▶# inew #─────────┘
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## ##
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#########
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2018-12-15 11:00:35 +03:00
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*/
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template SMTVerifierSM() {
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signal input is0;
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signal input levIns;
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signal input fnc;
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signal input prev_top;
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signal input prev_i0;
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signal input prev_iold;
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signal input prev_inew;
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signal input prev_na;
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signal output st_top;
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signal output st_i0;
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signal output st_iold;
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signal output st_inew;
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signal output st_na;
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signal prev_top_lev_ins;
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signal prev_top_lev_ins_fnc;
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prev_top_lev_ins <== prev_top * levIns;
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prev_top_lev_ins_fnc <== prev_top_lev_ins*fnc; // prev_top * levIns * fnc
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2018-12-15 11:15:58 +03:00
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// st_top = prev_top * (1-levIns)
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2018-12-15 11:00:35 +03:00
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// = + prev_top
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// - prev_top * levIns
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2018-12-15 11:15:58 +03:00
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st_top <== prev_top - prev_top_lev_ins;
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2018-12-15 11:00:35 +03:00
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// st_inew = prev_top * levIns * (1-fnc)
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// = + prev_top * levIns
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// - prev_top * levIns * fnc
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st_inew <== prev_top_lev_ins - prev_top_lev_ins_fnc;
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// st_iold = prev_top * levIns * (1-is0)*fnc
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// = + prev_top * levIns * fnc
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// - prev_top * levIns * fnc * is0
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st_iold <== prev_top_lev_ins_fnc * (1 - is0);
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// st_i0 = prev_top * levIns * is0
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// = + prev_top * levIns * is0
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st_i0 <== prev_top_lev_ins * is0;
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st_na <== prev_na + prev_inew + prev_iold + prev_i0;
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}
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